11 q-tech corporation - 10150 w. jefferson boulevard, culver city 90232 - tel: 310-836-7900 - fax: 310-836-2157 - www.q-t e c h . c o m q-tech corporation transistor outline packages to-5 and to-8 crystal clock oscillators 1.8 to 15vdc - 0.045hz to 125mhz transistor outline packages (revision a, may 2008) (eco# 9304) description q-techs transistor outline package crystal oscillators consist of a source clock square wave generator, logic output buffers and/or logic divider stages, and a round at high-precision quartz crystal built in an all metal to package. features ? made in the usa ? eccn: ear99 ? dfars (berry amendment) compliant ? usml registration # m17677 ? wide frequency range from 0.045hz to 125mhz ? available as qpl mil-prf-55310/09 and/10 (ttl) and /12 (cmos) ? choice of to packages and pin outs ? choice of supply voltages ? choice of output logic options ( cmos, acmos, hcmos, lvhcmos, and ttl) ? at-cut crystal ? all metal hermetically sealed package ? tight or custom symmetry available ? low height available ? external tuning capacitor option ? fundamental and third overtone designs ? tristate function option d ? three-point crystal mounts ? custom design available tailors to meet customers needs ? q-tech does not use pure lead or pure tin in its products ? rohs compliant applications ? designed to meet todays requirements for all voltage applications ? wide military clock applications ? industrial controls ? microcontroller driver model # ordering information qtxx xx d xx m 60.000mhz output frequency screened to mil-prf-55310,level b (left blank if no screening) 1 = 100ppm at 0oc to +70oc 3 ** = 5ppm at 0oc to +50oc 4 = 50ppm at 0oc to +70oc 5 = 25ppm at -20oc to +70oc 6 = 50ppm at -55oc to +105oc 9 = 50ppm at -55oc to +125oc 10 = 100ppm at -55oc to +125oc 11 = 50ppm at -40oc to +85oc 12 = 100ppm at -40oc to +85oc tristate option d (left blank if no tristate) for non-standard requirements, contact q-tech corporation at sales@q-tech.com c = cmos +5v to +15v * ac = acmos +5v hc = hcmos +5v t = ttl +5v l = lvhcmos + 3.3v n = lvhcmos + 2.5v r = lvhcmos + 1.8v z = z output specifications subject to change without prior notice. all transistor outline packages are available in surface mount form. packaging options other options available for an additional charge ? standard packaging in black foam ? solder dip sn/pb 60/40% ? p. i. n. d. test ? lead trimming for frequency stability vs. temperature options not listed herein, please request a custom part number. (*) please specify supply voltage when ordering cmos (**) require an external capacitor
2 q-tech corporation - 10150 w. jefferson boulevard, culver city 90232 - tel: 310-836-7900 - fax: 310-836-2157 - www.q-t e c h . c o m q-tech corporation transistor outline packages to-5 and to-8 crystal clock oscillators 1.8 to 15vdc - 0.045hz to 125mhz transistor outline packages (revision a, may 2008) (eco# 9304) electrical characteristics parameters c ac hc t l (*) output freq. range (fo) qt1, 14 244hz 15mhz 732.4hz 85mhz 732.4hz 125mhz qt2 0.045hz 85mhz 0.045hz 85mhz qt3 732.4hz 85mhz 732.4hz 85mhz supply voltage (vdd) 5v ~ 15vdc 10% 5.0vdc 10% 3.3vdc 10% freq. stability (?f/?t) see option codes operating temp. (topr) see option codes storage temp. (tsto) -62oc to + 125oc operating supply current (idd) (no load) f and vdd dependent 3 ma max. at 5v up to 5mhz 25 ma max. at 15v up to 15mhz 20 ma max. - 0.045hz ~ < 16mhz 25 ma max. - 16mhz ~ < 40mhz 35 ma max. - 40mhz ~ < 60mhz 45 ma max. - 60mhz ~ 85mhz 3 ma max. - 0.045hz ~ < 500khz 6 ma max. - 500khz ~ < 16mhz 10 ma max. - 16mhz ~ < 32mhz 20 ma max. - 32mhz ~ < 60mhz 30 ma max. - 60mhz ~ < 100mhz 40 ma max. - 100mhz ~ 125mhz symmetry (50% of ouput waveform or 1.4vdc for ttl) 45/55% max. fo < 4mhz 40/60% max. fo 4mhz 45/55% max. fo < 12mhz 40/60% max. fo 12mhz rise and fall times (with typical load) 30ns max. (measured from 10% to 90%) 15ns max. fo < 15khz 6ns max. fo 15khz ~ 39.999mhz 3ns max. fo 40mhz ~ 125 mhz (measured from 10% to 90% cmos or from 0.8v to 2.0v ttl) output load 15pf // 10k? 10ttl fo < 20mhz 6ttl fo 20mhz 15pf // 10k? start-up time (tstup) 10ms max. output voltage (voh/vol) 0.9 x vdd min.; 0.1 x vdd max. 2.4v min.; 0.4v max. 0.9 x vdd min.; 0.1 x vdd max. output current (ioh/iol) 1ma typ. at 5v 6.8ma typ. at 15v 24ma 8 ma -1.6ma / ttl +40a / ttl 4ma . enable/disable tristate function pin 1 call for details vih 2.2v oscillation; vil 0.8v high impedance vih 0.7 x vdd oscillation; vil 0.3 x vdd high impedance jitter rms 1 (at 25oc) 8ps typ. - < 40mhz 5ps typ. - 40mhz 15ps typ. - < 40mhz 8ps typ. - 40mhz aging (at 70oc) 5ppm max. first year / 2ppm typ. per year thereafter (*) available in 2.5vdc (n) or 1.8vdc (r) z output logic can drive up to 200 pf load with typical 6ns rise & fall times (tr, tf) ecl, pecl, lvpecl are available. please contact q-tech for details.
33 q-tech corporation - 10150 w. jefferson boulevard, culver city 90232 - tel: 310-836-7900 - fax: 310-836-2157 - www.q-t e c h . c o m q-tech corporation transistor outline packages to-5 and to-8 crystal clock oscillators 1.8 to 15vdc - 0.045hz to 125mhz transistor outline packages (revision a, may 2008) (eco# 9304) package configuration versus pin connections (6.60) .260 .500 (12.70) (.457) .018 (5.08) .200 pin no. 1 (9.14) .360 freq. d/c s/n p/n q-tech max. min. a qt1 min. q-tech p/n freq. d/c s/n .360 (9.14) pin no. 1 .200 (5.08) .018 (.457) (12.70) .500 .175 (4.45) d qt14 q-tech p/n pin no. 1 .500 (12.70) .075 (1.91) .300 (7.62) (5.08) .200 freq. d/c s/n .018 (.457) .500 (12.70) min. max. b qt2 pin no. 1 (7.16) .282 (13.72) .540 q-tech p/n freq. d/c s/n .500 (12.70) min. (.457) .018 max. (7.62) .300 c qt3 qt # conf vcc gnd case output e/d ext. cap equivalent mil-prf-55310 configuration qt1 a 8 4 4 5 1 1 & 2 /09 = qt1t /12 = qt1c qt2 b 12 6 6 5 3 9 & 10 n/a qt3 c 8 4 4 5 1 1 & 2 /10 = qt3t /13 = qt3c qt14 d 8 4 4 5 1 1 & 2 n/a dimensions are in inches (mm)
44 q-tech corporation - 10150 w. jefferson boulevard, culver city 90232 - tel: 310-836-7900 - fax: 310-836-2157 - www.q-t e c h . c o m q-tech corporation transistor outline packages to-5 and to-8 crystal clock oscillators 1.8 to 15vdc - 0.045hz to 125mhz transistor outline packages (revision a, may 2008) (eco# 9304) 8 4 5 1 2 qt1t3 +5vdc gnd output 0.01uf 20pf(*) 6k 270 d1 d2 d3 d4 cext d1-d4: 1n4148 or equivalent (*) cl includes scope probe capacitance typical test circuit for qt1t3 (10ttl) frequency vs. temperature curve -50 -40 -30 -20 -10 10 20 30 40 0 -55 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 05 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100 105 110 115 120 125 sn2 sn3 sn4 sn1 frequency stability (ppm) frequency stability versus temperature qt1l -36mhz temperature (c) vdd gnd 0.1xvdd 0.9xvdd voh vol trt f th t 0.5xvdd symmetry = x 100% th t ts start-up box oscilloscope dut variable ramp 54616b agilent typical set-up for start-up time output waveform (typical) startup time supply current test circuit - - output ground vdd out gnd 0.1f 15pf e/d tristate function power supply 10k ma vdc + + + (*) or 0.01f (*) cl includes probe and jig capacitance typical test circuit for cmos logic 0 5 10 15 20 25 30 35 40 45 0.5 28 16 24 27 32 36 40 48 50 55 65 70 75 85 100 125 133 150 160 freq(mhz) icc (ma) typical supply current icc (ma) at 3.3vdc & 5.0vdc cmos logic no load icc 3.3v icc 5v power supply + - ma 0.1f vdc - vdd out out gnd typical test circuit for ttl logic. 0.01f rs (*) cl inclides the loading effect of the oscilloscope probe. e/d c l + + - rl load 6 ttl 10 ttl cl(*) 12pf 20pf rl 430 270 rs 10k 6k or vdd the tristate function on pin 1 has a built-in pull-up resistor typical 50k?, so it can be left floating or tied to vdd without deteriorating the electrical performance.
55 q-tech corporation - 10150 w. jefferson boulevard, culver city 90232 - tel: 310-836-7900 - fax: 310-836-2157 - www.q-t e c h . c o m q-tech corporation transistor outline packages to-5 and to-8 crystal clock oscillators 1.8 to 15vdc - 0.045hz to 125mhz transistor outline packages (revision a, may 2008) (eco# 9304) 45o 45o hybrid case substrate die d/a epoxy d/a epoxy heat die r1 d/a epoxy substrate d/a epoxy hybrid case r2 r3 r4 r5 thermal characteristics ja jc ca die t t t c a j ca jc (figure 1) (figure 2) the heat transfer model in a hybrid package is described in figure 1. heat spreading occurs when heat flows into a material layer of increased cross-sectional area. it is adequate to assume that spreading occurs at a 45 angle. the total thermal resistance is calculated by summing the thermal resistances of each material in the thermal path between the device and hybrid case. rt = r1 + r2 + r3 + r4 + r5 the total thermal resistance rt (see figure 2) between the heat source (die) to the hybrid case is the theta junction to case (theta jc) inc/w. ? theta junction to case (theta jc) for this product is 30c/w. ? theta case to ambient (theta ca) for this part is 100c/w. ? theta junction to ambient (theta ja) is 130c/w. maximum power dissipation pd for this package at 25c is: ? pd(max) = (tj (max) C ta)/theta ja ? with tj = 175c (maximum junction temperature of die) ? pd(max) = (175 C 25)/130 = 1.15w environmental specifications q-tech standard screening/qci (mil-prf55310) is available for all of our transistor outline packages. q-tech can also customize screening and test procedures to meet your specific requirements. the transistor outline packages are designed and processed to exceed the following test conditions: environmental test test conditions temperature cycling mil-std-883, method 1010, cond. b constant acceleration mil-std-883, method 2001, cond. a, y1 seal fine leak mil-std-883, method 1014, cond. a burn-in 160 hours, 125c with load aging 30 days, 70c vibration sinusoidal mil-std-202, method 204, cond. d shock, non operating mil-std-202, method 213, cond. i thermal shock, non operating mil-std-202, method 107, cond. b ambient pressure, non operating mil-std-202, 105, cond. c, 5 minutes dwell time minimum resistance to solder heat mil-std-202, method 210, cond. c moisture resistance mil-std-202, method 106 terminal strength mil-std-202, method 211, cond. c resistance to solvents mil-std-202, method 215 solderability mil-std-202, method 208 please contact q-tech for higher shock requirements
66 q-tech corporation - 10150 w. jefferson boulevard, culver city 90232 - tel: 310-836-7900 - fax: 310-836-2157 - www.q-t e c h . c o m q-tech corporation transistor outline packages to-5 and to-8 crystal clock oscillators 1.8 to 15vdc - 0.045hz to 125mhz transistor outline packages (revision a, may 2008) (eco# 9304) phase noise is measured in the frequency domain, and is expressed as a ratio of signal power to noise power measured in a 1hz bandwidth at an offset frequency from the carrier, e.g. 10hz, 100hz, 1khz, 10khz, 100khz, etc. phase noise measurement is made with an agilent e5052a signal source analyzer (ssa) with built-in outstanding low-noise dc power supply source. the dc source is floated from the ground and isolated from external noise to ensure accuracy and repeatability. in order to determine the total noise power over a certain frequency range (bandwidth), the time domain must be analyzed in the frequency domain, and then reconstructed in the time domain into an rms value with the unwanted frequencies excluded. this may be done by converting l(f) back to s(f) over the bandwidth of interest, integrating and performing some calculations. the value of rms jitter over the bandwidth of interest, e.g. 10khz to 20mhz, 10hz to 20mhz, represents 1 standard deviation of phase jitter contributed by the noise in that defined bandwidth. figure below shows a typical phase noise/phase jitter of a qt1acd10m, 5.0vdc, 40mhz clock at offset frequencies 10hz to 5mhz, and phase jitter integrated over the bandwidth of 12khz to 1mhz. phase noise and phase jitter integration period jitter as data rates increase, effects of jitter become critical with its budgets tighter. jitter is the deviation of a timing event of a signal from its ideal position. jitter is complex and is composed of both random and deterministic jitter components. random jitter (rj) is theoretically unbounded and gaussian in distribution. deterministic jitter (dj) is bounded and does not follow any predictable distribution. dj is also referred to as systematic jitter. a technique to measure period jitter (rms) one standard deviation (1) and peak-to-peak jitter in time domain is to use a high sampling rate (>8g samples/s) digitizing oscilloscope. figure shows an example of peak-to-peak jitter and rms jitter (1) of a qt1acd-40mhz, at 5.0vdc. rms jitter (1): 4.89ps peak-to-peak jitter: 44.4ps symbol definition l(f) integrated single side band phase noise (dbc) s (f)=(180/)x 2 l(f)df spectral density of phase modulation, also known as rms phase error (in degrees rms jitter = s (f)/(fosc.360) jitter(in seconds) due to phase noise. note s (f) in degrees. qt1acd10m, 5.0vdc - 40mhz
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